Operating regions & DC bias
A transistor equation is valid only after the operating region is known — yet the operating region itself depends on the solved terminal voltages. Build a solve-then-check workflow for NPN BJT, n-channel JFET and enhancement nMOS. Classify BJT regions from its two junction biases, derive JFET cutoff/ohmic/pinch-off conditions with an explicit VP sign convention, derive long-channel MOS cutoff/triode/saturation conditions, then solve one bias network for each family and reject algebraic roots that violate their own model assumptions.
- Classify NPN BJT cutoff, forward-active, saturation and reverse-active operation from base-emitter and base-collector junction biases rather than from one memorized VCE number.
- Use a forward-active BJT bias model only after verifying the solved collector-base junction is reverse biased.
- Derive a voltage-divider/emitter-resistor BJT bias equation using the Thévenin equivalent seen by the base and show how emitter feedback reduces dependence on β.
- State the n-channel JFET sign convention VP<0 and distinguish cutoff, ohmic/linear and pinch-off/saturation regions.
- Solve a JFET self-bias circuit from VGS=−IDRS and the declared transfer model, then reject mathematical roots outside VP≤VGS≤0.
- State the enhancement nMOS long-channel cutoff, triode and saturation inequalities using overdrive VOV=VGS−VTH.
- Solve a source-degenerated MOS DC bias equation and reject roots that make VOV≤0 or violate the assumed saturation condition VDS≥VOV.
- Explain why a transistor DC solution is incomplete until terminal voltages, branch currents, region inequalities and power signs are independently checked.
- Distinguish physical operating-region boundaries from compact numerical rules such as VBE≈0.7 V or VCE,sat≈0.2 V.
- Compare emitter/source degeneration as negative feedback that converts current changes into control-voltage changes opposing the original perturbation.
A transistor model predicts currents only inside a declared operating region. Bias analysis therefore has a circular-looking structure: assume a region, solve the circuit, then verify that the solved terminal voltages actually satisfy that region.
02.1BJT regions come from the two junction biases
For an NPN BJT define VBE=VB−VE and VBC=VB−VC. The two p–n junctions determine the qualitative region:
The common VBE≈0.7 V and VCE,sat≈0.2 V rules are compact approximations for selected silicon devices and currents. Region classification is more fundamentally a junction-bias statement.
02.2Divider bias with emitter degeneration
Figure 2.1 — BJT divider bias with emitter degeneration
The one question is: what control voltage follows from the DC network, and which region inequality must then be checked?
Replace the base divider by its Thévenin equivalent VTH,RTH. Under a constant-VBE and constant-β forward-active model,
so
Then compute VE=IER E, VC=VCC−ICRC and VCE=VC−VE. The assumed active model is accepted only if the collector-base junction is reverse biased, equivalently VC>VB for this NPN convention.
Emitter resistance provides negative feedback: if current rises, VE rises, reducing VBE for a nearly fixed base drive. When (β+1)RE dominates RTH, current becomes less sensitive to β.
02.3Worked BJT bias check
Take VCC=12 V, VTH=3.0 V, RTH=20 kΩ, RE=1 kΩ, RC=2 kΩ, β=100 and VBE=0.70 V.
Since VC>VB, the collector-base junction is reverse biased and the forward-active assumption is self-consistent.
02.4JFET regions with an explicit sign convention
For the n-channel JFET model used here, VP=VGS(off)<0. The transfer approximation in the pinch-off/saturation region is
Cutoff occurs in this compact model for VGS≤VP. For an established channel, the low-VDS region is approximately ohmic. Pinch-off/saturation requires approximately
The term “pinch-off” does not mean zero drain current; it marks the onset of the approximately current-source-like region in this first model.
02.5JFET self-bias solves VGS and ID together
Figure 2.2 — JFET self-bias
The one question is: what control voltage follows from the DC network, and which region inequality must then be checked?
With IG≈0 and gate tied to ground through RG, VG≈0. Therefore
Insert this into the transfer model and solve for ID. Example: IDSS=8 mA, VP=−4 V, RS=1 kΩ gives the admissible root ID=2 mA, hence VGS=−2 V.
With VDD=12 V and RD=1 kΩ, VD=10 V, VS=2 V and VDS=8 V. Since VGS−VP=2 V and VDS≥2 V, the assumed saturation model is consistent.
Any additional algebraic root outside VP≤VGS≤0 must be rejected even if it satisfies the squared equation numerically.
02.6Long-channel enhancement nMOS regions
Define overdrive VOV=VGS−VTH. In the simplest long-channel strong-inversion model:
With k=μnCox(W/L), the corresponding first-order current equations are
These relations neglect subthreshold conduction, mobility degradation, channel-length modulation and short-channel effects.
02.7MOS source degeneration can produce multiple algebraic roots
Figure 2.3 — nMOS bias with source degeneration
The one question is: what control voltage follows from the DC network, and which region inequality must then be checked?
Let VG be fixed by a high-resistance gate-bias network and IG≈0. Then VS=IDRS and
Assuming saturation,
Example: VG=5 V, VTH=1 V, RS=1 kΩ, k=1 mA/V² gives algebraic roots 2 mA and 8 mA. The 8 mA root implies VGS=−3 V, so VOV<0 and contradicts the assumed saturation model. Reject it. The physical model-consistent root is ID=2 mA.
With VDD=12 V and RD=1 kΩ: VS=2 V, VD=10 V, VDS=8 V and VOV=2 V, so VDS≥VOV and saturation is self-consistent.
02.8Bias stabilization is negative feedback
Emitter/source degeneration uses the same physical logic in different devices: a rise in current raises VE or VS. For a fixed or stiff control-node voltage, that reduces VBE or VGS, opposing the current increase.
This does not make BJT, JFET and MOSFET laws identical. It is a circuit-level feedback pattern acting on different device physics.
02.9Universal solve–check workflow
- Declare terminal references and candidate operating region.
- Write only the equations valid in that region.
- Solve the DC network.
- Recover every terminal voltage and current.
- Check the region inequalities independently.
- Reject inconsistent algebraic roots and re-solve with another region if necessary.
- Check power signs, ratings and model scope.
A numerically valid root of an assumed equation is not automatically a physically valid transistor operating point.
02.10Mastery exercises
- For an NPN with VB=0.75 V, VE=0 V, VC=5 V, classify the two junction biases qualitatively.
- Using the BJT example above, verify VC−VB and state the region check.
- For IDSS=8 mA, VP=−4 V, what does the JFET transfer model predict at VGS=−2 V?
- For that JFET, what minimum VDS satisfies the simple saturation inequality?
- For an nMOS with VTH=1 V, VGS=3 V, VDS=0.5 V, identify the region.
- For the same MOSFET with VDS=4 V, identify the region.
- Why must the 8 mA algebraic root in the worked MOS example be rejected?
- Explain in one sentence how source/emitter resistance provides negative feedback.
Solutions
1. BE is forward biased and BC is reverse biased, so forward active is consistent.
2. VC−VB≈5.58 V>0; collector-base remains reverse biased.
3. 8 mA(1−(−2)/(−4))²=2 mA.
4. VGS−VP=−2−(−4)=2 V.
5. VOV=2 V and VDS<VOV, so triode.
6. VDS≥VOV, so saturation in the long-channel model.
7. It implies VGS below threshold, contradicting the saturation equation used to obtain it.
8. A current increase raises emitter/source voltage and thereby reduces the controlling junction/gate-to-source voltage for a stiff input node.
Chapter 03 will differentiate these device laws at Q and derive transconductance, showing exactly how bias sets small-signal control strength.