A. S. Sedra & K. C. Smith, Microelectronic Circuits — BJT and MOSFET device/model chapters.
Terminal variables, operating mechanisms, DC bias, transconductance and small-signal modeling.
AE-01
Course overview
BJT, JFET & MOSFET fundamentals, bias and small-signal models
AE-01 builds transistor reasoning from device terminals and control physics to operating regions, DC bias, transconductance and small-signal models. BJT, JFET and MOSFET are compared without forcing them into one fictitious universal transistor law.
5 chapters5 available · 0 plannedintermediate
Prerequisites
- AE-00 — diodes & nonlinear circuits
- CT-01 — Thévenin/Norton
- DY-01 — first-order dynamics
By the end of the course
- Compare BJT, JFET and MOSFET from device physics and terminal variables.
- Find physically admissible DC bias points.
- Derive and use gm rather than memorizing isolated gain formulas.
- Build small-signal models around Q.
- Calculate input/output resistance and diagnose model limits.
Syllabus
Five readings from device families to small-signal models.
AE-01 builds transistor reasoning from device terminals and control physics to operating regions, DC bias, transconductance and small-signal models. BJT, JFET and MOSFET are compared without forcing them into one fictitious universal transistor law.
- 01→
BJT, JFET & MOSFET device families
Compare three transistor families from terminal variables and physical control mechanisms before amplifier configurations. Treat the BJT as an injection-controlled bipolar device with finite base current, the JFET as a depletion-controlled field-effect channel with a reverse-biased p-n gate, and the MOSFET as an insulated-gate field-effect device whose gate voltage controls surface charge. Define terminal currents and control voltages, separate ideal DC input-current statements from real leakage and dynamic capacitance, and establish what is shared — three-terminal control and local transconductance — versus what is fundamentally different.
190–240 min · Intermediate · available - 02→
Operating regions & DC bias
A transistor equation is valid only after the operating region is known — yet the operating region itself depends on the solved terminal voltages. Build a solve-then-check workflow for NPN BJT, n-channel JFET and enhancement nMOS. Classify BJT regions from its two junction biases, derive JFET cutoff/ohmic/pinch-off conditions with an explicit VP sign convention, derive long-channel MOS cutoff/triode/saturation conditions, then solve one bias network for each family and reject algebraic roots that violate their own model assumptions.
205–260 min · Intermediate · available - 03→
Transconductance & control variables
Turn each transistor’s nonlinear transfer law into a local control strength at its DC operating point. Define gm as a partial derivative with the output voltage held fixed, derive gm=IC/VT for the exponential BJT model, derive the JFET gm relation from the Shockley transfer curve with VP<0, and derive gm=kVOV=2ID/VOV for the long-channel saturated MOSFET. Compare gm/ID, distinguish intrinsic device gm from the effective transconductance seen through source/emitter degeneration, and quantify when a local linear approximation stops being accurate.
190–245 min · Intermediate · available - 04→
Small-signal models
Linearize the full transistor around a verified DC operating point and turn local derivatives into circuit elements. Build the BJT hybrid-π model from gm and β, derive rπ=β/gm, add output resistance ro when Early effect matters, construct JFET/MOS low-frequency models from gm and go, and show how independent DC supplies become AC ground while controlled sources remain active. Connect these equivalent circuits to the Jacobian of the nonlinear device equations and state when capacitances, body effect and frequency dependence must be added.
205–260 min · Intermediate · available - 05→
Input/output resistance & model limits
Finish AE-01 by turning the small-signal models into measurable port properties and by making every major approximation explicit. Define input and output resistance with test sources, derive BJT base resistance with emitter degeneration, show why a FET gate can have very high low-frequency intrinsic resistance while the bias network still sets the circuit input resistance, derive simple output-resistance combinations with ro, then map the boundaries of constant-β, Early, long-channel square-law, ideal-gate, low-frequency and small-signal assumptions. Use the result as the bridge into actual amplifier stages in AE-02.
195–250 min · Intermediate · available
Reference backbone
References used
The course combines semiconductor-device physics with circuit-oriented compact models and keeps every approximation tied to its operating region.
B. Razavi, Fundamentals of Microelectronics — transistor fundamentals and bias chapters.
Physical intuition, device equations, bias and transition from large-signal to small-signal analysis.
A. Agarwal & J. H. Lang, Foundations of Analog and Digital Electronic Circuits — MOS and bipolar device modeling.
Model hierarchy, circuit-oriented device laws and local linearization.
MIT OpenCourseWare 6.012 — Microelectronic Devices and Circuits.
Semiconductor-device physics for p-n junctions, MOS structures, MOSFETs and BJTs.
MIT OpenCourseWare 6.002 — Circuits and Electronics.
Circuit-level transistor models, biasing and small-signal reasoning.
R. L. Boylestad & L. Nashelsky, Electronic Devices and Circuit Theory — JFET/MOSFET/BJT chapters.
JFET transfer characteristics, terminal conventions and comparative device behavior.