Input/output resistance & model limits

For a linearized small-signal network, apply a test voltage vt at the port and calculate the resulting current it entering the network:

When finding output resistance, zero the independent input increments while keeping dependent sources active. A DC voltage supply is already AC ground in the small-signal network; a DC current source is open only if its incremental value is zero.

This definition is safer than visual inspection whenever a controlled source or feedback path remains in the network.

In the low-frequency hybrid-π model, it=ib and vπ=ib rπ. With emitter resistor RE unbypassed,

The input test voltage is

Hence, under the stated assumptions,

This is a circuit result, not an intrinsic transistor parameter. If RE is bypassed by a capacitor whose impedance is negligible in the band of interest, the reflected term largely disappears and rin,b approaches rπ.

If the BJT base is biased by resistors R1 and R2 connected to ideal DC rails, those rails become AC ground. The signal source therefore sees

Example: rπ=2.5 kΩ, β=99 and RE=1 kΩ gives rin,b=102.5 kΩ. If R1∥R2=20 kΩ, the actual circuit input resistance is only about 16.7 kΩ. Quoting the transistor’s rπ alone would badly overstate the source loading.

In the ideal low-frequency JFET/MOS intrinsic model, ig≈0, so the intrinsic gate input resistance tends to infinity. But a real amplifier still needs a bias path.

for a common two-resistor gate divider when gate leakage is neglected. At higher frequency, gate capacitances create a complex input impedance rather than a purely resistive infinite input.

For JFETs, reverse-junction leakage also limits the real DC input resistance; for MOSFETs, dielectric leakage and protection structures make the real gate non-ideal.

For the simplified common-source incremental stage shown, the input is zero so vgs=0. The controlled source remains in the model but its controlling voltage is zero; therefore its current is zero. The test port sees

The same structure appears for a common-emitter stage with emitter AC-grounded: Rout≈RC∥ro under the corresponding unilateral low-frequency assumptions.

With source/emitter degeneration or feedback from output to input, vgs or vπ need not remain zero under an output test. Then Rout must be solved from the full controlled-source circuit rather than guessed from parallel resistors.

Confusing ro with Rout or rπ with Rin is one of the most common early small-signal mistakes.

• BJT β: β varies with collector current, temperature, device and operating region. Constant β is a local engineering approximation.
• BJT exponential/Early model: high-level injection, quasi-saturation, breakdown and self-heating require richer models.
• JFET transfer law: the square transfer relation is a compact model over a defined region; leakage, output slope and device-specific behavior remain.
• MOS square law: mobility degradation, velocity saturation, channel-length modulation, body effect, subthreshold conduction and short-channel electrostatics can dominate modern devices.

A more complicated model is useful only if its parameters are known and the required accuracy justifies it.

The first-order model neglects Taylor terms beyond the Jacobian. It is valid only while the signal excursion is small enough that parameter variation over the excursion is acceptable.

Frequency also matters. At higher frequency, Cπ/Cμ for BJTs and Cgs/Cgd plus junction capacitances for FETs create poles, zeros and feedback. Interconnect/package parasitics eventually become part of the circuit.

The safe workflow is therefore not “small signal = use hybrid-π forever,” but:

1. Are all current and voltage references declared on a real schematic?
2. Does the DC solution satisfy the assumed operating-region inequalities?
3. Are gm, rπ and ro evaluated at that Q-point?
4. Is the input/output port definition explicit?
5. Were independent sources zeroed correctly while dependent sources remained active?
6. Are coupling/bypass capacitors justified as opens, impedances or shorts at the actual frequency?
7. Is the signal excursion small enough for local linearization?
8. Are β, VA, λ, VTH, VP or other compact parameters valid in this range?
9. Do temperature, leakage, breakdown, noise or power dissipation matter?
10. Would a higher-order device model change the engineering conclusion?

1. For rπ=3 kΩ, β=99 and RE=470 Ω, find rin,b.
2. If R1∥R2=30 kΩ, find the circuit Rin from exercise 1.
3. An ideal low-frequency MOS gate is biased by 1 MΩ to AC ground. What is the approximate circuit Rin if gate leakage/capacitance are neglected?
4. For RD=10 kΩ and ro=50 kΩ with vgs=0, find Rout.
5. Why must a gm vgs source remain in the output-resistance test circuit even if its numerical current becomes zero?
6. Name four effects that invalidate a simple long-channel MOS square-law model.
7. Why can a bypass capacitor make Rin frequency dependent?
8. State the difference between ro and Rout in one sentence.

AE-01 is now conceptually complete. AE-02 can begin actual amplifier stages with a disciplined chain: bias first, model second, port loading third, gain and swing only after those checks.