Gain, loading & output swing

Define v_s at the source, v_i at the amplifier input, and v_o at the load. Then separate input transfer from stage gain:

Quoting A_stage while the source sees severe input attenuation overstates the usable source-to-load gain.

If the source has resistance R_s and the amplifier presents small-signal input resistance R_in, the simplest divider gives

For a MOS stage R_in is usually set by the gate-bias network at low frequency, not by DC gate conduction. For a BJT stage it also includes r_π and any bias network. Coupling capacitors add frequency dependence outside the assumed midband range.

For the actively loaded MOS stage of chapter 04, the unloaded incremental resistance is approximately r_o,n∥r_o,p. Connecting R_L changes the same node:

The same structure applies to a CE stage after replacing its input and output model elements by the corresponding BJT quantities.

Let the valid output interval be V_min≤v_out≤V_max. For the complementary MOS active-load stage, the first long-channel saturation estimate is

For resistor-loaded stages the upper and lower boundaries follow from the load line and the transistor region limits. For BJTs they follow from cutoff/saturation or, more rigorously, the junction-bias conditions.

If V_OQ is the quiescent output voltage, the largest region-limited symmetric peak excursion is

If the only goal were symmetric voltage swing, the geometric midpoint would be

Real bias networks, required current, distortion and common-mode constraints can prevent choosing that point freely. Mid-supply is not a universal optimum when headroom is asymmetric.

Using the local loaded gain only as a first estimate,

This does not prove low distortion at that amplitude. Transistor transfer laws are nonlinear, so a conservative linear signal is usually smaller. The formula is a consistency bound linking a local derivative to a large-signal region limit.

Take VDD=5 V, VOV,n=0.25 V, |VOV,p|=0.30 V, gm=5 mS, ro,n=100 kΩ, ro,p=120 kΩ, RL=50 kΩ, Rin=200 kΩ and Rs=20 kΩ.

The region window is approximately 0.25 V to 4.70 V. Its midpoint is 2.475 V and the symmetric region-limited output amplitude there is 2.225 V peak. The corresponding first estimates are about 17.1 mV peak at the amplifier input and 18.8 mV peak at the source. A practical low-distortion limit would be chosen smaller and checked with the nonlinear model or simulation.

Lower-side clipping can indicate the amplifying device is losing saturation/forward-active headroom; upper-side clipping can indicate the load device is leaving its current-source-like region. Asymmetric clipping therefore carries information about Q placement and the two different compliance margins.

If the measured small-signal gain is lower than predicted before clipping, first check source attenuation, external loading, finite ro and degeneration before blaming transistor gm.

1. Choose supply, topology and target bias current.
2. Solve DC bias and verify every transistor region.
3. Compute the large-signal output window.
4. Linearize at the actual Q-point and obtain gm, rπ where relevant, and ro.
5. Include source resistance, bias-network input resistance and external load.
6. Derive source-to-load gain from the complete small-signal circuit.
7. Translate output headroom back to allowable input amplitude.
8. Check distortion, power and parameter sensitivity; then iterate Q/current/component values.

1. Rs=10 kΩ and Rin=40 kΩ. Find αin.
2. ro,n=60 kΩ, ro,p=90 kΩ and RL=30 kΩ. Find Rout,L.
3. If gm=3 mS for problem 2, find Astage and then ASL using problem 1.
4. Vmin=0.30 V, Vmax=4.40 V and VOQ=2.0 V. Find maximum symmetric region-limited output peak.
5. Where should VOQ be placed for symmetric region margins in problem 4?
6. If |ASL|=40 and available output peak is 1.2 V, estimate the source peak limit.

AE-02 is now conceptually closed: device models became biased stages, buffers, mirrors, active loads and finally an end-to-end gain/headroom design workflow.