04 · Intermediate

Active loads

Replace passive collector/drain resistors by transistor current-source loads and derive why the incremental load resistance can become much larger than a practical resistor. Use complementary PNP/PMOS active loads, connect them to current mirrors, derive gain as gm times the parallel output resistances, then expose the price paid in compliance voltage, matching and finite output swing.

195–250 minIntermediate

In this lesson

Draw canonical NPN-with-PNP and nMOS-with-pMOS actively loaded gain stages using true transistor symbols and explicit supply/output nodes.
Explain why a bias transistor can behave as a high incremental resistance while carrying a finite DC current.
Derive the first-order actively loaded common-emitter gain Av≈−gm,n(ro,n∥ro,p) under the stated unilateral low-frequency assumptions.
Derive the analogous common-source gain Av≈−gm,n(ro,n∥ro,p) for complementary MOS active loading.
Relate ro to Early voltage or channel-length modulation so active-load gain is tied to device physics rather than an ideal current-source symbol.
Compare the resistor-loaded and active-loaded gains at equal bias current and explain why the active load can provide a much larger effective load resistance.
State the compliance/headroom conditions required simultaneously by the amplifying transistor and the active-load transistor.
Show how output swing becomes bounded by the saturation/active-region requirements of both devices.
Explain how current-mirror mismatch and finite output resistance perturb the intended bias current and gain.
Use limiting cases ro→∞, gm→0 and shrinking supply voltage to check the model and identify where idealized gain claims become physically impossible.

Starting question

A large voltage gain needs a large incremental resistance at the output node. A passive resistor can provide it, but at finite DC current it also consumes a DC voltage drop. An active load separates these roles more effectively: it carries the bias current while presenting a much larger small-signal resistance.

04.1DC current and incremental resistance are different questions

For a resistor, one R sets both DC drop and incremental resistance. For a transistor in a current-source-like region, finite DC current can coexist with a small output-current slope.

r_o = 1 / [(∂I/∂V_out) at Q]

An active load is therefore not an ideal current source. Early effect or channel-length modulation makes r_o finite.

04.2Complementary MOS active load

Figure 4.1 — nMOS common-source stage with pMOS active load

The one question is: how can Q2 carry the DC bias current yet present a large incremental resistance at the output node?

Q1 provides transconductance. Q2 establishes bias current and contributes mainly its output resistance when its gate and source are held at AC-fixed potentials.

Q1 is the signal transistor. Q2 is biased so its DC current approximately equals the desired Q1 current. If Q2 source and gate are AC fixed, its incremental gate-to-source voltage is approximately zero; its finite r_o,p remains at the output node.

04.3Derive gain from output-node KCL

Figure 4.3 — Small-signal reduction at the output node

The one question is: why do the two output resistances appear in parallel rather than in series?

VDD and Q2 bias are AC grounds. Both drains share vout, so each output resistance connects the same node to AC ground.

g_m,nv_gs + v_o/r_o,n + v_o/r_o,p = 0

A_v = v_o/v_gs = −g_m,n(r_o,n ∥ r_o,p)

The two output resistances are parallel because both connect vout to AC ground. With external load R_L, use r_o,n ∥ r_o,p ∥ R_L. If Q2 bias is not AC stiff, its controlled-current response must also be included.

04.4Headroom: high incremental resistance is not free

Both MOSFETs must remain in the saturation region used to obtain high output resistance.

Q1: v_o ≥ V_OV,n

Q2: V_DD − v_o ≥ |V_OV,p|

V_OV,n ≤ v_o ≤ V_DD − |V_OV,p|

This is a region-valid large-signal window, not a guarantee of low distortion. The gain formula is a local derivative around Q.

04.5BJT analogue: PNP current-source load

Figure 4.2 — NPN common-emitter stage with PNP active load

The one question is: what small-signal resistance does the shared collector node see while both transistors remain forward active?

The upper PNP replaces the collector resistor. VBP may come from a mirror or bias network and must be sufficiently AC-stiff for the model used here.

With an AC-stiff PNP bias, an NPN common-emitter stage sees approximately r_o,n ∥ r_o,p at the shared collector node.

A_v ≈ −g_m,n(r_o,n ∥ r_o,p)

r_o ≈ V_A/I_C (first Early-effect estimate)

The rigorous headroom check comes from junction biases: both BJTs must remain in forward active operation. A fixed VCE,sat rule is only an approximation.

04.6Resistor load versus active load at equal DC current

Take VDD=5 V, ID=0.5 mA and Vout,Q=2.5 V. A passive drain resistor is R_D=5 kΩ. With g_m=5 mS and r_o,n=100 kΩ, the first-order resistor-loaded gain is about −23.8 V/V.

Replacing R_D by a pMOS load with r_o,p=120 kΩ gives:

R_out = 100 kΩ ∥ 120 kΩ ≈ 54.5 kΩ

A_v ≈ −0.005 × 54.5 kΩ ≈ −273 V/V

The much larger value is a local first-order result, not a promise of usable 273× large-signal swing.

04.7Finite output resistance, mismatch and bias errors

r_o,p ≈ 1/(λ_pI_D,Q)

A mirror-generated active load inherits mirror nonidealities: unequal drain voltages, finite output resistance, device mismatch, temperature gradients and finite bias-node impedance all perturb the intended current and gain.

Keep three checks separate: DC-current accuracy, region/compliance validity, and incremental output resistance at the actual Q-point.

04.8Gain and output swing must be designed together

For VDD=5 V, VOV,n=0.25 V and |VOV,p|=0.30 V, the simple saturation window is approximately 0.25 V ≤ vout ≤ 4.70 V. Around a 2.5 V Q-point, the nearest region boundary is about 2.2 V away, but a low-distortion signal normally uses much less than that.

High intrinsic gain with almost no headroom is not a useful voltage amplifier. Active-load design is a gain–headroom–current trade.

04.9Model checks and common traps

Do not set r_o=∞ unless that limit is explicitly assumed.
Do not add r_o,n and r_o,p in series at the common output node.
Do not use the high-gain formula after either transistor leaves its assumed region.
Do not call a bias node AC ground unless its incremental impedance justifies it.
Do not infer output swing from small-signal gain alone.

04.10Mastery exercises

For gm=4 mS, ro,n=80 kΩ and ro,p=120 kΩ, compute unloaded gain.
Add RL=20 kΩ and recompute.
For VDD=3.3 V, VOV,n=0.20 V and |VOV,p|=0.25 V, write the simple saturation window.
Why does gm,p not appear in the simplest gain formula?
If λ doubles at fixed ID, what happens to ro?
Why is a 100 kΩ incremental active-load resistance feasible at 0.5 mA from a few-volt supply while a literal 100 kΩ drain resistor is not?

Solutions

1. 80 kΩ ∥ 120 kΩ=48 kΩ, so Av≈−192 V/V.

2. 48 kΩ ∥ 20 kΩ≈14.12 kΩ, so Av≈−56.5 V/V.

3. Approximately 0.20 V≤vout≤3.05 V.

4. Its incremental control voltage is approximately zero when gate and source are AC fixed.

5. ro halves.

6. A 100 kΩ resistor at 0.5 mA would need 50 V DC drop; a biased transistor can have that local slope with only its compliance voltage.

Chapter 05 combines gain, loading and output swing in one design workflow.