Current mirrors
Build BJT and MOS current mirrors from matched transistor laws rather than treating them as ideal current sources. Derive the BJT base-current error, area scaling, compliance and Early-effect output resistance; derive MOS current-ratio scaling, saturation/compliance and channel-length-modulation error; then connect mismatch and temperature to practical bias accuracy.
- Draw the canonical NPN and nMOS sink mirrors with a diode-connected reference device and an explicit output terminal.
- Derive why equal VBE in matched BJTs gives equal ideal collector currents before base-current and Early corrections.
- Derive Iout=Iref/(1+2/β) for the matched two-transistor BJT mirror under the stated assumptions.
- Generalize the BJT mirror to an emitter-area ratio N and derive Iout/Iref=N/[1+(N+1)/β].
- State the BJT output-compliance requirement as a region condition and explain why saturation destroys current mirroring.
- Relate finite BJT output slope to Early effect and ro≈VA/IC.
- Derive the long-channel MOS mirror ratio Iout/Iref=k2/k1≈(W/L)2/(W/L)1 for matched process parameters and ideal gate current.
- State the MOS compliance requirement Vout≥VOV for the output device in the simple saturation model.
- Include channel-length modulation to show why unequal VDS values create mirror error and finite output resistance.
- Explain how device mismatch, temperature gradients and resistor/reference errors limit practical current accuracy.
A current mirror is often drawn as an ideal current source in a larger amplifier. What circuit actually creates that current, why is the copied current only approximate, and how much output-voltage range is required before the mirror stops behaving like a current source?
03.1BJT mirror: one VBE, two collector currents
Figure 3.1 — Basic NPN current mirror
The one question is: how does Q1 turn Iref into a common VBE for Q1 and Q2?
Q1 is diode-connected: collector and base are tied. Q1 and Q2 therefore share the same VBE, but the reference current must also supply both base currents.
Q1 is diode-connected, so its collector-base node adjusts until the reference branch current is compatible with its VBE. The same base-emitter voltage appears on Q2.
For matched transistors in the ideal forward-active exponential model,
so the ideal collector currents are equal. Equality comes from matching plus equal VBE—not from a magical current-copy element.
03.2Finite β creates a systematic BJT mirror error
For equal β and matched collector currents IC, the reference branch must supply Q1 collector current and two base currents:
Therefore
At β=100 and Iref=1 mA, Iout≈0.9804 mA. Even perfectly matched transistors do not copy the full reference current when finite base currents are supplied from the reference node.
03.3Emitter-area scaling sets a current ratio
If Q2 has N times the emitter area of Q1 and both share VBE, the ideal collector current ratio is approximately N. With equal β, let IC2=N IC1. Then
and
For N=4 and β=100, the ratio is 4/1.05≈3.81 rather than exactly 4.
03.4BJT compliance and Early effect
Q2 mirrors correctly only while it remains in the region assumed by the model. For an NPN sink mirror, the collector voltage must stay high enough that Q2 does not enter saturation. A region check is more fundamental than memorizing one universal VCE,sat number.
Finite Early effect makes collector current depend on VCE. Locally,
so a simple mirror has finite output resistance rather than the infinite output resistance of an ideal current source. With VA=100 V and IC=1 mA, ro≈100 kΩ.
The resistor-set reference itself is also implicit:
and VBE depends on current and temperature, so Rref does not create a temperature-independent exact current.
03.5MOS mirror: equal VGS, geometry-scaled current
Figure 3.2 — Basic nMOS current mirror
The one question is: why does the same VGS produce a current ratio set by k2/k1?
M1 is diode-connected: gate=drain. M1 and M2 share the same VGS. With ideal zero gate current, Iref flows essentially through M1.
For long-channel enhancement nMOS devices in saturation, ignoring channel-length modulation,
M1 is diode-connected and shares its gate with M2, so both have the same VGS and VOV. Ideal gate current is zero, hence Iref≈ID1. Therefore
If M2 has four times W/L and Iref=0.5 mA, the ideal copied current is 2 mA.
03.6MOS compliance is the saturation inequality
The output device M2 must stay in saturation:
With the source at ground, this becomes approximately
Below that voltage M2 enters triode, and the current becomes strongly dependent on Vout. This minimum output voltage is the mirror’s compliance/headroom cost in the simple model.
The diode-connected M1 satisfies the saturation inequality automatically whenever it is on because VDS1=VGS and VTH>0.
03.7Channel-length modulation creates ratio error
Include the first output-slope correction:
Then, for otherwise matched devices,
Thus matching VGS is not enough for perfect current matching when VDS differs. The same effect produces finite output resistance
For λ=0.02 V⁻¹, VDS1=1.5 V and VDS2=5 V, the output/reference ratio is multiplied by about 1.10/1.03≈1.068: roughly a 6.8% error from output-voltage mismatch alone.
03.8Mismatch and temperature are part of the mirror model
Mirroring depends on matched device parameters. Real devices differ in saturation current, β, VTH, mobility factor, geometry and local temperature.
For a square-law MOS mirror at common VGS, a small overdrive mismatch gives approximately
so low-overdrive operation can be especially sensitive to threshold mismatch. Layout, device area and thermal symmetry therefore matter in integrated mirrors.
For discrete mirrors, thermal coupling and device selection can dominate accuracy; textbook “matched” assumptions should not be silently transferred to unrelated discrete parts.
03.9A mirror is a bias block with finite headroom and Rout
In the next chapter, these non-ideal current sources become active loads. Their large output resistance can increase voltage gain, but their compliance voltage consumes output-swing headroom.
03.10Mastery exercises
- A matched BJT mirror has β=50 and Iref=1 mA. Find Iout ignoring Early effect.
- For β=100 and area ratio N=3, find Iout/Iref.
- At IC=0.5 mA and VA=80 V, estimate BJT mirror output resistance.
- A MOS mirror has (W/L)2/(W/L)1=5 and Iref=200 μA. Find ideal Iout.
- If VOV=0.25 V, what minimum Vout keeps the simple nMOS output device in saturation?
- For λ=0.01 V⁻¹, VDS1=1 V and VDS2=6 V, compute the channel-length-modulation ratio factor.
- Why does a BJT mirror have a base-current error but an ideal MOS mirror does not have the analogous gate-current error?
- Name three practical mismatch/temperature mechanisms that limit mirror accuracy.
Solutions
1. Iout=1 mA/(1+2/50)=0.9615 mA.
2. Ratio=3/[1+4/100]=3/1.04≈2.885.
3. ro≈80 V/0.5 mA=160 kΩ.
4. Iout=1.0 mA.
5. Approximately 0.25 V in the stated long-channel model.
6. (1.06)/(1.01)≈1.0495, about +4.95%.
7. BJT base terminals require finite carrier current; the ideal insulated MOS gates draw zero DC current.
8. Examples: VTH/IS mismatch, β/mobility mismatch, geometry error, thermal gradients, resistor/reference error.
Chapter 04 will turn mirrors into active loads and show why replacing a resistor by a high-output-resistance transistor can raise gain while reducing available voltage headroom.