Common-emitter & common-source stages
Build the two canonical inverting voltage-amplifier stages from complete DC-biased circuits, not memorized gain formulas. Separate DC bias from midband AC, replace supplies by AC ground and coupling/bypass capacitors by their justified midband equivalents, then derive voltage gain from the verified hybrid-π/FET small-signal models. Include transistor output resistance, load resistance, input-divider loading, source resistance and emitter/source degeneration as explicit circuit effects rather than hidden corrections.
- Start from complete DC-biased common-emitter and common-source circuits and identify the Q-point quantities that must remain inside the intended operating region.
- State the midband assumptions under which coupling and bypass capacitors may be replaced by shorts while DC supplies become AC ground.
- Draw the MAJAL small-signal equivalent before writing any gain equation.
- Derive the BJT common-emitter gain from base-emitter incremental voltage: vo/vπ=−gm(RC∥RL∥ro) when the emitter is at AC ground.
- Include source resistance and the base-bias network to derive the source-to-output gain as input attenuation times intrinsic stage gain.
- Derive the MOS common-source gain vo/vgs=−gm(RD∥RL∥ro) when the source is at AC ground.
- Show that ideal MOS gate current does not remove attenuation caused by the gate-bias network and source resistance.
- Derive the effect of unbypassed emitter/source degeneration on gain using KCL/KVL rather than inserting a memorized denominator.
- Separate gain from headroom: the small-signal gain is local around Q and must not predict excursions that cross cutoff/triode/saturation boundaries.
- Validate numerical examples by checking units, sign inversion, limiting cases gm→0, load→∞ and degeneration→0.
Why do common-emitter and common-source stages invert voltage, and exactly which resistance sets their gain? The answer appears only after the DC operating point and the real midband small-signal circuit are separated correctly.
01.1Begin with the biased circuit, not the gain formula
Figure 1.1 — Common-emitter: complete circuit before linearization
The one question is: which elements establish Q and which elements carry the midband signal?
R1–R2, RC and RE establish the DC operating point. Cin/Cout isolate DC levels. CE may be treated as a short only after its impedance is shown negligible in the frequency range of interest.
The transistor must first have a valid Q-point in forward active operation. RC, RE and the divider R1–R2 establish the DC conditions; Cin and Cout block DC between stages; CE changes only the AC emitter impedance when its reactance is small enough.
A midband approximation therefore requires all of the following:
- the transistor remains near its verified Q-point;
- |ZCin| and |ZCout| are small compared with the relevant signal-path resistances;
- |ZCE| is small compared with the emitter impedance we intend to bypass;
- internal transistor capacitances are still negligible;
- the signal amplitude is small enough for the local transistor model.
Only under those conditions may DC supplies become AC ground and the selected capacitors become approximate shorts.
01.2Common-emitter gain from output-node KCL
Figure 1.2 — Common-emitter: actual midband small-signal circuit
The one question is: where do input attenuation and gm·vπ current conversion appear?
The emitter is AC ground only if CE is effectively a short in the band. RB=R1∥R2 loads the source; RC, RL and ro load the output node.
Define the output loading
With the emitter at AC ground, vπ is the base-emitter increment. At the output node the controlled source gm vπ pulls current toward the emitter/ground. KCL gives
hence
The minus sign is physical: increasing vπ increases collector current, increasing the drop through the collector load and therefore lowering collector voltage.
01.3The source rarely delivers all of vs to vπ
With the emitter bypassed, the small-signal input resistance at the base node is
For a source resistance Rsig,
Therefore the source-to-output gain is
This separates two distinct mechanisms: transistor conversion gain and passive input attenuation.
01.4Worked common-emitter midband example
Let gm=40 mS, rπ=2.5 kΩ, RC=4.7 kΩ, RL=10 kΩ, ro=50 kΩ, RB=47 kΩ and Rsig=1 kΩ.
The input resistance is
so
A gain magnitude of 84.6 does not imply that a 1 V source signal is allowed: the small-signal/Q-point swing constraint must be checked separately.
01.5Common-source: the same circuit logic, different input physics
Figure 1.3 — Common-source: complete circuit before linearization
The one question is: how does the gate network establish VG when ideal DC gate current is negligible?
The RG1–RG2 divider establishes VG without requiring ideal gate current. RD and RS, together with the MOS model, establish Q. CS bypasses RS in small signal only where |ZCS| is sufficiently small.
The MOS stage has the same architectural roles—bias, transconductance, drain load and optional source bypass—but the device input is a field-controlled gate rather than a forward-biased junction.
At DC, ideal gate current is approximately zero, so the divider sets
Then the source resistor and MOS transfer law determine ID and VGS. The solved point must satisfy the intended region condition before the small-signal model is used.
01.6Common-source gain from the same output-node argument
Figure 1.4 — Common-source: actual midband small-signal circuit
The one question is: why does an open intrinsic gate not necessarily make the circuit input infinite?
The intrinsic gate draws no current in this model, but RG=RG1∥RG2 provides a path to AC ground and therefore loads the signal generator.
With the source AC-grounded by a valid bypass approximation, define
Output-node KCL gives
For the external source, ideal gate current is zero but the gate bias network is not absent:
01.7Worked common-source example
Let gm=5 mS, RD=6.8 kΩ, RL=20 kΩ, ro=100 kΩ, RG=1 MΩ and Rsig=10 kΩ.
The gate-divider attenuation is
so the source-to-output gain is approximately
The high MOS input resistance makes source attenuation small here, but that conclusion comes from the numerical bias-network impedance, not from a slogan that the gate is “infinite resistance.”
01.8Unbypassed emitter/source resistance reduces gain by local feedback
For the BJT, neglect ro for this derivation and leave RE unbypassed. The emitter current is
so
With RC′=RC∥RL under the same simplified assumptions,
For a FET with ro neglected and unbypassed RS, id=gmvgs and vg=vgs+idRS, giving
Degeneration trades gain for reduced sensitivity and improved local linearity; it does not merely “waste voltage.”
01.9Gain is local; headroom is a separate large-signal constraint
The gain formulas predict infinitesimal behavior around Q. A finite output excursion must remain inside the operating region used to derive the model.
- BJT: avoid excursions that drive the collector-base junction forward or push the device into cutoff.
- MOS: keep the device in the intended saturation/triode region throughout the required swing.
- Check collector/drain resistor voltage drops, emitter/source voltage movement and the load current simultaneously.
Chapter 05 will turn this into an explicit gain/loading/output-swing design workflow.
01.10Mastery exercises
- Derive vo/vπ for a bypassed common-emitter stage with RC=3.3 kΩ, RL=10 kΩ, ro→∞ and gm=30 mS.
- If RB=20 kΩ, rπ=2 kΩ and Rsig=1 kΩ, find vπ/vs.
- Combine exercises 1–2 for the total source-to-output gain.
- For a common-source stage with gm=4 mS, RD=5.6 kΩ, RL=22 kΩ and ro=80 kΩ, find vo/vgs.
- Why can a MOS stage with ig≈0 still have finite Rin?
- What condition justifies replacing an emitter-bypass capacitor by a short?
- Show that the degenerated MOS gain tends to −(RD∥RL)/RS when gmRS≫1 and ro is neglected.
- Why is a calculated gain of −100 not sufficient to claim a 2 V input can produce −200 V output?
Solutions
1. RC′=3.3 kΩ∥10 kΩ≈2.481 kΩ, so vo/vπ≈−0.03·2481≈−74.4.
2. Rin=20 kΩ∥2 kΩ≈1.818 kΩ; vπ/vs≈1.818/(1+1.818)≈0.645.
3. Approximately −48.0.
4. RD′≈5.6 kΩ∥22 kΩ∥80 kΩ≈4.24 kΩ, so vo/vgs≈−17.0.
5. The gate-bias resistors and any external network provide finite paths even when intrinsic gate current is neglected.
6. Its reactance magnitude must be negligible compared with the emitter impedance it bypasses over the frequency band of interest.
7. Divide numerator and denominator by gm: −(RD∥RL)/(RS+1/gm)→−(RD∥RL)/RS.
8. Small-signal gain is local around Q; supply rails and transistor operating-region boundaries limit finite swing.
Chapter 02 will turn the transistor around: emitter/source followers sacrifice voltage gain to obtain buffering, high input resistance and low output resistance.