AoNArt of Nanoelectronics
My space
05 · Foundational → intermediate

Designing a source for a real load

Turn an allowed loading error into a source-resistance requirement without introducing device models too early.

45–60 minFoundational → intermediate
In this lesson
  • Derive loading error directly from the Thévenin source–load relation.
  • Translate a voltage-accuracy specification into a maximum allowed source resistance.
  • Design for a range of loads instead of one nominal value.
  • Separate what a port model predicts from how an active circuit will later realize that port.
Starting question

A source should deliver approximately 5 V to any load of 10 kΩ or more. How small must its output resistance be if the loading error must stay below 1%?

This is a pure source–load design problem. No transistor model is needed: the same reasoning will later be reused when active devices are introduced in Volume II.

requirement → impedance ratioworst load → source design

05.1Write the loaded-source relation first

For a Thévenin source feeding a resistive load, the source resistance and load form a divider:

VL = VTH · RL/(RTH + RL)
IL = VTH/(RTH + RL)

Figure 5.1 — Design from the load backwards

A real source is represented by VTH and RTH. The worst-case load RL,min sets the largest loading error.

verified source–load topology
Thévenin equivalent with load+−VTH5 VRTH100 ΩRL10 kΩVOUTGND
The current arrow fixes the positive load-current direction; the voltage arrow points toward the positive load terminal.

05.2Turn a voltage-accuracy requirement into an impedance requirement

Define the fractional loading error relative to the open-circuit voltage:

ε = (VTH − VL)/VTH
ε = RTH/(RTH + RL)

Solving for the source resistance gives the design inequality

RTH ≤ ε/(1 − ε) · RL,min

05.3Worked design — 1% maximum error

Let VTH = 5.00 V, RL,min = 10 kΩ and εmax = 0.01.

RTH,max = 0.01/0.99 · 10 kΩ = 101 Ω

Choosing 100 Ω satisfies the requirement. At the worst-case load,

VL = 5 · 10 000/(10 000 + 100) = 4.9505 V
ε = 0.990%
IL = 0.495 mA

05.4Design for a load range, not for one nominal value

RLVLloading error
10 kΩ4.9505 V0.990%
100 kΩ4.9950 V0.100%
1 MΩ4.9995 V0.010%

The smallest expected load is the critical case. Designing only for a nominal load can hide a failure at the edge of the allowed range.

05.5What Thévenin does — and does not — tell you about the physical source

A low RTH means the terminal voltage is insensitive to load current. Thévenin does not tell us how the internal circuit achieves that low output resistance, how much power it consumes, or whether it saturates under large current.

Those questions lead to active electronics. Later in Volume II, AoN will introduce diodes, BJT, JFET and MOSFET devices before using them in bias networks, buffers and amplifiers. Only then will we reuse Thévenin inside those circuits.

05.6Retrieval check

A 20 kΩ minimum load must see less than 2% loading error. What is the largest allowed RTH?
Solution. RTH ≤ 0.02/0.98 × 20 kΩ ≈ 408 Ω.
If RL doubles while VTH and RTH stay fixed, what happens to VL?
Answer. VL increases toward VTH because the load draws less current and causes less drop across RTH.

Chapter 06 now compares the Thévenin and Norton source forms and asks a different design question: when is maximum power transfer useful?

Preview chapter 06
Volume ITable of contents