Transistor high-frequency models
Extend the low-frequency BJT and MOS small-signal models by adding the charge-storage paths that become electrically active as frequency rises. Derive how Cπ/Cμ or Cgs/Cgd/Cdb create frequency-dependent input and output currents, distinguish current-gain pole fβ from transition frequency fT, and keep intrinsic device speed separate from the bandwidth of a complete amplifier that also contains source, load and feedback impedances.
- Explain why a midband small-signal transistor model fails when charge-storage currents become comparable to conductive small-signal currents.
- Draw the BJT high-frequency hybrid-π model with rπ, gm·vπ, ro, Cπ and Cμ connected to the correct physical nodes.
- Write frequency-domain base and collector current relations for the BJT high-frequency model under an explicit terminal-voltage convention.
- Derive the one-pole short-circuit current-gain form and distinguish fβ from the unity-current-gain transition frequency fT.
- Draw the MOS high-frequency small-signal model with gm·vgs, ro, Cgs, Cgd and a stated body/junction-capacitance assumption.
- Write the MOS gate current as displacement current through Cgs and Cgd and derive the first-order intrinsic fT approximation under short-circuit-output assumptions.
- Explain why Cπ, Cμ, Cgs, Cgd and junction capacitances depend on device bias, geometry and operating region rather than being universal constants.
- Distinguish transistor fT from amplifier −3 dB bandwidth, closed-loop bandwidth and maximum useful oscillation frequency.
- Explain why a capacitance connecting input and output nodes is qualitatively different from a capacitance tied only to AC ground.
- Apply a validity workflow: choose Q-point → linearize conductances → add charge-storage elements → include external impedances → derive the relevant transfer/current gain → check approximations.
A transistor can be perfectly linearized around its bias point and still fail to behave like its midband small-signal model. The missing physics is charge storage: as frequency rises, the currents required to move charge through internal capacitances become comparable to the conductive small-signal currents. AE-04 starts by adding those physical paths before discussing amplifier poles.
01.1High-frequency model means small signal plus charge storage
The low-frequency BJT/MOS models from AE-01 are local derivatives of terminal currents with respect to terminal voltages. At higher frequency we must also linearize stored terminal charge. For a small perturbation, a charge derivative creates a capacitance and therefore a displacement current.
The symbol C in a high-frequency transistor model is therefore not automatically a fixed geometric capacitor. It is generally an incremental quantity evaluated at the operating point and can change with bias and operating region.
01.2BJT: add Cπ and Cμ to the hybrid-π model
Figure 1.1 — BJT high-frequency hybrid-π model
The one question is: which new current paths appear when internal charge storage can no longer be neglected?
Cπ connects base to emitter; Cμ connects base directly to collector. Cμ is therefore an input-to-output coupling path and will become central to the Miller effect. The whole network is a local small-signal model around one stated Q-point.
For a forward-active BJT, Cπ represents the incremental base-emitter charge-storage path, including diffusion charge and junction contributions in the chosen model. Cμ is the reverse-biased collector-base depletion capacitance. The conductive parameters remain
but those parameters now coexist with capacitive current paths. In particular, Cμ directly bridges the input and output nodes.
01.3Write currents from the actual node voltages
Let vπ=vb−ve and vμ=vb−vc. With currents defined leaving the base through the intrinsic model, the input current contains the resistive and capacitive terms
The collector terminal also receives the controlled-current contribution gm vπ, the ro current and the opposite terminal current of Cμ. Writing currents from terminal voltages prevents a common mistake: replacing Cμ by an arbitrary capacitance to ground before the circuit gain between base and collector is known.
01.4From the BJT model to fβ and fT
To define short-circuit current gain, set the collector to AC ground relative to the emitter. Then Cπ and Cμ both load the base. If the direct Cμ feedthrough term in the collector-current numerator and ro are neglected in the first-order model,
The exact unity magnitude of this one-pole approximation is
Thus fβ is the pole of current gain in this reduced model, while fT is the frequency at which the magnitude of short-circuit current gain falls to unity. They are not synonyms.
01.5Worked BJT speed estimate
Take gm=40 mS, rπ=2.5 kΩ, Cπ=20 pF and Cμ=1 pF. Then β0=100 and
A 303 MHz transistor does not imply a 303 MHz common-emitter amplifier. Source resistance, collector resistance, load capacitance and especially input-output coupling through Cμ can produce a much lower stage pole.
01.6MOS: gate current reappears as displacement current
Figure 1.2 — MOS high-frequency small-signal model
The one question is: why can a gate with negligible DC current demand substantial AC current?
Gate current charges Cgs and Cgd. Cgd couples input and output; Cdb is shown here as a drain-junction capacitance to a body held at AC ground. These are differential capacitances around Q and vary with bias and operating region.
For the simplified model shown, the gate current is
This reconciles two statements that are often confused: the insulated MOS gate can have negligible DC conduction current, yet its AC source must continuously charge and discharge the gate capacitances.
The drain-body and source-body junction capacitances are also bias dependent. In integrated circuits the bulk connection and substrate network determine which node each junction capacitance sees in the small-signal circuit.
01.7First-order MOS transition-frequency estimate
With the drain AC-short to the source, Cgs and Cgd both load the gate. In the common first-order intrinsic estimate, neglecting gate resistance, ro and the Cgd feedthrough term in the output-current numerator,
For gm=10 mS, Cgs=0.50 pF and Cgd=0.10 pF, this estimate gives fT≈2.65 GHz. It is a device metric under a stated test condition, not an amplifier bandwidth specification.
01.8Why Cμ and Cgd are special
A capacitance from one node to AC ground loads that node according to its local impedance. A capacitance between input and output responds to the voltage difference across two moving nodes:
If vout is an amplified and inverted version of vin, the capacitor current seen at the input can be much larger than sCvin. Chapter 03 will derive that multiplication exactly as the Miller effect; here the important point is topological: do not ground an input-output capacitance prematurely.
01.9Device fT is not stage bandwidth
The complete amplifier includes source resistance, bias network impedances, load resistance/capacitance, transistor output resistance and input-output feedback capacitance. Its poles must be derived from that network.
01.10Mastery exercises
- A BJT has gm=25 mS, β0=125, Cπ=18 pF and Cμ=2 pF. Find rπ, fβ and the first-order fT estimate.
- For the same BJT with vc not at AC ground, write the Cμ current leaving the base.
- A MOSFET has gm=8 mS, Cgs=0.7 pF and Cgd=0.1 pF. Estimate intrinsic fT under the stated first-order assumptions.
- Why can a MOS gate draw almost zero DC current but substantial current at 500 MHz?
- Why is replacing Cgd by a capacitor to ground before solving the stage gain generally unsafe?
- Name two reasons a common-source amplifier bandwidth can be far below transistor fT.
Solutions
1. rπ=β0/gm=5 kΩ. fβ=1/[2π·5 kΩ·20 pF]≈1.59 MHz. fT≈gm/[2π·20 pF]≈199 MHz.
2. iCμ,b=sCμ(vb−vc) with the stated current direction.
3. fT≈8 mS/[2π·0.8 pF]≈1.59 GHz.
4. DC conduction and displacement current are different mechanisms; ig≈jωC·v grows with frequency.
5. Cgd senses vg−vd; vd moves with gain and phase, so its apparent input loading depends on the circuit transfer.
6. Examples: source/bias resistance with input capacitance, Miller multiplication of Cgd/Cμ, finite output resistance with load capacitance, or additional internal poles.
Chapter 02 will turn these capacitances and node resistances into amplifier poles and zeros instead of assigning a bandwidth by inspection.