Ideal & non-ideal op-amps
Build the operational-amplifier abstraction from a differential-input, single-ended-output voltage amplifier before using any virtual-short shortcut. Define the open-loop law vo=A(s)(v+−v−), then separate ideal assumptions from real limits: finite open-loop gain, finite input/output resistance, input offset and bias currents, common-mode range, CMRR, output swing/current limits, slew rate and frequency dependence. Show explicitly that v+≈v− is a consequence of stable negative feedback with large loop gain and unsaturated operation — not an intrinsic op-amp law.
- Draw the canonical op-amp symbol with explicit non-inverting input, inverting input, output and supply rails before writing any equation.
- Define the open-loop differential relation vo=A0(v+−v−) for a low-frequency finite-gain model and explain why it is not a closed-loop formula.
- State the ideal op-amp assumptions A0→∞, Rin→∞, Rout→0, zero offset/bias currents and unlimited output only as mathematical idealizations.
- Derive the finite-gain error of a voltage follower and show quantitatively how v+−v− approaches zero when A0 is large and the output is not saturated.
- Explain why v+=v− is not generally valid in open loop, positive feedback, saturation or during large-signal slew limiting.
- Model finite differential input resistance and finite output resistance using an explicit equivalent circuit and identify how source/load impedances create error.
- Define input offset voltage, input bias current and input offset current and show how source resistance converts input current into an output-referred error through the closed-loop gain.
- Distinguish differential input voltage from common-mode input voltage and define CMRR as the ratio of differential to common-mode gain under a stated frequency condition.
- Treat common-mode input range, output-voltage swing and output-current limit as independent large-signal constraints that must all be checked.
- Introduce finite gain bandwidth and slew rate as distinct small-signal/large-signal dynamic limits while deferring detailed pole/stability derivations to AE-04.
An op-amp is first a high-gain differential voltage amplifier. The familiar ideal rules become useful only after the feedback connection, operating region and required accuracy have been checked.
02.1Open-loop law and terminal variables
Figure 2.1 — Op-amp terminals
The one question is: which variables belong to the open-loop model?
The + and − marks are attached to the non-inverting and inverting pins. Supply rails constrain operation but are not signal inputs.
A0 is the low-frequency differential open-loop gain. This is not a closed-loop equation and cannot demand output voltage beyond the available supply-dependent swing.
02.2Ideal assumptions are mathematical limits
A practical ideal model also ignores common-mode, output-current, output-swing and dynamic limits. The input-current rule follows from Rin→∞. By contrast, v+≈v− is not an intrinsic op-amp law; it emerges from a stable negative-feedback loop with sufficiently large loop gain and linear operation.
02.3Finite gain explains the follower error
Figure 2.3 — Follower: the virtual short is a loop result
The one question is: how does feedback make v+−v− small?
The output returns to the inverting input. With stable negative feedback, large A0 and unsaturated operation, only a very small differential error is needed to create the output.
For A0=100000 and vs=1 V, vo≈0.999990 V and vd≈10 μV. If the required output exceeds the available swing, the amplifier saturates and this linear result no longer applies.
02.4Finite Rin and Rout are circuit elements
Figure 2.2 — Low-frequency non-ideal equivalent
The one question is: where do finite A0, Rin and Rout enter?
Rin loads the inputs differentially. The dependent source generates A0(v+−v−), then Rout separates the internal node from the output. Offset, saturation and dynamics are not yet included.
The first non-ideal equivalent loads the differential input through Rin and represents the output by an internal controlled source plus series Rout. With a load RL in the isolated output model,
Feedback can later change the effective closed-loop input/output resistances; chapter 04 derives that effect from loop gain.
02.5Offset voltage and input currents create DC error
Input offset voltage VOS models the differential mismatch referred to the input under a stated test convention. Input bias and offset currents are commonly summarized by
An input current through source resistance RS creates an error of order IBRS; the closed-loop noise gain then maps the equivalent input error to the output. High source resistance can therefore make very small bias currents important.
02.6Common-mode gain and CMRR
CMRR is frequency dependent and does not guarantee that vcm lies inside the allowed input common-mode range.
02.7Three independent large-signal checks
- Input common-mode range: the input stage must remain correctly biased.
- Output-voltage swing: the output stage needs supply headroom under the actual load.
- Output-current limit: sourcing/sinking current must remain within capability.
A closed-loop equation can be algebraically correct and still request a physically impossible operating point.
02.8Bandwidth and slew rate are different limits
The dominant-pole model describes small-signal frequency response; slew rate is a large-signal derivative limit. Detailed pole/phase-margin analysis is deferred to AE-04 and chapter 05.
02.9Gate before using v+≈v−
- Identify a negative-feedback path.
- Verify input common-mode, output swing and output-current limits.
- Verify the loop is stable over the relevant range.
- Check that loop gain is large enough for the required accuracy.
- Only then use v+≈v− and negligible input current as approximations.
This prevents applying a virtual short to an open-loop comparator, a positive-feedback circuit or a saturated amplifier.
02.10Mastery exercises
- A follower has A0=2×10⁵ and vs=2 V. Find vo and vd.
- If its output swing is only ±1.5 V, explain why exercise 1 becomes invalid physically.
- A0=10⁵ and Rin=2 MΩ. Find the differential input current at vd=100 μV.
- Rout=50 Ω, internal source 5 V, RL=1 kΩ: find terminal vo.
- Ad=2×10⁵ and CMRR=100 dB: estimate Acm.
- IB=50 nA through 100 kΩ: estimate input-referred voltage error.
- SR=0.5 V/μs: largest 20 kHz sine peak before slew limiting?
- State four conditions required before using v+≈v−.
Solutions
1. vo≈1.999990 V; vd≈10 μV.
2. The requested output exceeds the physical swing, so saturation invalidates the linear solution.
3. 50 pA.
4. 5×1000/1050≈4.762 V.
5. 100 dB means CMRR=10⁵, so Acm≈2.
6. 5 mV.
7. Vp≤0.5×10⁶/(2π·20×10³)≈3.98 V.
8. Negative feedback, stability, linear/non-saturated operation, and sufficiently large loop gain; all input/output ranges must also be valid.
Chapter 03 derives negative feedback as a general loop structure instead of an op-amp-specific trick.