01 · Introductory

Nodes, branches and loops

Circuit topology comes before equations: know what is connected to what.

75–100 minIntroductory
In this lesson
  • Define node, branch, path and loop.
  • Recognize when points belong to the same ideal node.
  • Count branch currents without double-counting wires.
  • Separate topology from component values.
Starting question

Before writing any equation, can you look at a circuit drawing and say exactly which terminals are electrically the same point?

Kirchhoff's laws act on connectivity, not on the artistic shape of the drawing. A wire may bend across half the page and still represent one ideal node; two wires may cross visually and still be electrically separate if there is no junction.

01.1Topology is the connectivity skeleton of the circuit

Circuit topology answers a deliberately stripped-down question: what is connected to what? It ignores resistor values, source amplitudes, physical wire length and page geometry unless those features change electrical connection.

Two drawings with different shapes can therefore represent the same circuit if each component terminal belongs to the same electrical node in both drawings.

01.2Node: one connected conductor set, one node potential

For the early lumped model, a node is a maximal set of terminals and ideal-wire points connected together without an intervening circuit element. All points in that set share one node potential.

“Maximal” matters: if two wire segments are directly connected, we do not invent separate node names merely because the line turns a corner or passes through several drawing segments.

A junction of three or more element terminals is often called an essential node in circuit textbooks. The distinction becomes useful in nodal analysis, but an ordinary two-terminal connection is still a node.

Three component terminals are connected by one uninterrupted ideal conductor. How many node potentials exist there?
One. The whole conductor set is one ideal node, even if it is drawn with several line segments.

01.3Branch: define the convention before counting

Textbooks use the word branch with slightly different levels of generality. In early AoN DC analysis, a branch is a two-terminal circuit element connecting two nodes, carrying one branch current. Thus a resistor, ideal voltage source or ideal current source is one branch.

An ideal wire segment is not counted as a resistor-like branch merely because it is drawn separately. Later graph-theoretic treatments may group series elements or define branches more abstractly; when we do that, the convention will be stated explicitly.

01.4Path, closed path, loop and mesh

A path is an ordered sequence of connected branches. A closed path returns to its starting node. In introductory circuit analysis, a loop is a closed path that does not pass through a node more than once, except for the start/end node.

A mesh is more restrictive: in a planar drawing, it is a loop that does not contain another loop inside it. Mesh analysis will use that extra property later; KVL itself can be written around any valid loop.

01.5Worked topology reading

Figure 1.1 — Read connectivity before equations

Deliberately free of calculation arrows: three electrically distinct nodes connect four elements. Wire length and bends do not create extra nodes.

verified topology
Loaded voltage divider+−VS12 VR12 kΩR23 kΩRL6 kΩVINVOUTGND
The one question in this figure is: how many nodes and branches, independent of component values?

Ignore the numerical values first. The verified circuit has three distinct electrical nodes:

  1. the source-top / R1-input node;
  2. VOUT, joining R1, R2 and RL;
  3. GND, joining the source return, R2 and RL.

Using the early AoN branch convention, the four two-terminal elements—source, R1, R2 and RL—are four branches.

Nnodes=3
Nbranches=4

Changing R2 from 3 kΩ to 30 kΩ changes the circuit equations and currents, but it does not change this topology.

01.6Series and parallel can already be read topologically

Without yet deriving equivalent-resistance formulas, topology already tells us the structural conditions:

  • Two two-terminal elements are in parallel if both of their terminals connect to the same two nodes.
  • Two elements form an unbranched series connection when they share a node that has no other branch attached, so the same branch current must pass through both.

In Figure 1.1, R2 and RL are parallel because both connect VOUT to GND. R1 is not in simple series with either of them because VOUT is a branching node.

DC-03 will derive the familiar series/parallel formulas from Kirchhoff and Ohm rather than treating these observations as memorized shortcuts.

01.7Redrawing without changing the circuit

A powerful analysis habit is to redraw a circuit for clarity while preserving node membership. You may move a component on the page, straighten a wire or stretch a node visually; none of that changes the circuit if every terminal remains connected to the same node as before.

A safe redraw procedure is:

  1. name or mentally identify each electrical node;
  2. list the pair of nodes connected by every element;
  3. redraw the nodes in a clearer geometry;
  4. reconnect each element to the same node pair;
  5. only then restore values and variable arrows.

01.8Practice for mastery

  1. Does replacing a 1 kΩ resistor by 10 kΩ change circuit topology? Explain.
  2. Two resistors share one terminal, but a third branch also connects to that same node. Are the two resistors in simple series?
  3. Two components connect between node A and node B, even though one is drawn above the other. What topological relation do they have?
  4. Why can a wire crossing be dangerous to interpret from appearance alone?
  5. For Figure 1.1, list the node pair connected by each of the four branches.
Solutions

1. No. Only a component value changes.

2. No. The shared node branches, so the same current is not forced through both elements.

3. They are in parallel.

4. A graphical crossing may or may not be an electrical junction; the schematic's junction convention must decide connectivity.

5. Source: input node–GND; R1: input node–VOUT; R2: VOUT–GND; RL: VOUT–GND.

With nodes and branches now unambiguous, the next chapter can state KCL as a charge-balance equation at a node rather than as a memorized slogan.