01

Engineering problem

A 12 V source feeds R1 = 3 kΩ in series with a node where R2 = 6 kΩ goes to ground. A load RL = 4.7 kΩ will later be connected from VOUT to ground. Before connecting the load, determine the Thévenin and Norton equivalents seen at VOUT. Then use each equivalent to predict the loaded voltage and current.

ValuesVS = 12 VR1 = 3 kΩR2 = 6 kΩRL = 4.7 kΩ

Original loaded network

The load is connected here only for the final equivalence check. Remove RL conceptually when extracting VTH and RTH.

ERC + connectivity verified
Loaded voltage divider+−VS12 VR13 kΩR26 kΩRL4.7 kΩVINVOUTGND
02

What this exercise should prove

01

Interpret Thévenin/Norton as equivalent terminal behavior rather than algebraic tricks.

02

Find VTH from the open-circuit voltage.

03

Find RTH by deactivating the independent voltage source.

04

Convert exactly between Thévenin and Norton forms.

05

Verify that the original, Thévenin and Norton circuits predict the same loaded operating point.

03

Derivation checkpoint

ThéveninVTH = VOC = VS · R2/(R1 + R2)RTH = R1 || R2VTH = 8.000 VRTH = 2.000 kΩ
NortonIN = VTH/RTHRN = RTHIN = 4.000 mARN = 2.000 kΩ
04

Two drawings, one terminal law

Thévenin form

Same port behavior represented by an ideal voltage source in series with RTH.

ERC + connectivity verified
Thévenin equivalent with load+−VTH8 VRTH2 kΩRL4.7 kΩVOUTGND

Norton form

Same port behavior represented by an ideal current source in parallel with RN = RTH.

ERC + connectivity verified
Norton equivalent with loadIN4 mARN2 kΩRL4.7 kΩVOUTGND
05

Understand → Calculate → Transform → Verify → Explain

01

Understand

Treat everything to the left of the load terminals as a one-port. Ask what voltage/current law the load sees.

02

Calculate

Remove RL, compute VOC = VTH, then zero the 12 V source and look back into the port to find RTH.

03

Transform

Compute IN = VTH/RTH and draw the Norton source in parallel with RN = RTH.

04

Verify

Reconnect RL and compute VL and IL from both equivalents. The results must match.

05

Explain

Explain why internal circuits with different drawings can still be indistinguishable from the load.

06

Questions

  1. What is the open-circuit voltage at VOUT?
  2. After deactivating the 12 V ideal source, what resistance is seen looking into VOUT?
  3. What Norton current corresponds to the Thévenin equivalent?
  4. What voltage appears across RL = 4.7 kΩ?
  5. What load current flows?
  6. Why do the Thévenin and Norton drawings look different but predict the same terminal behavior?
Hints

Progressive hints

Reveal hint 1

With RL removed, R1 and R2 form an ordinary divider.

Reveal hint 2

When an ideal voltage source is set to 0 V, replace it by a short circuit.

Reveal hint 3

After that short, R1 and R2 are both connected from VOUT to ground.

Reveal hint 4

Use IN = VTH/RTH for the Norton form.

Go further

Go further

The detailed course derives the terminal law, covers dependent sources and test-source methods, solves multi-node resistor networks, then applies Thévenin to real source–load design and measurement loading.

Open the detailed Thévenin/Norton course
07

Common misconceptions

01

Leaving RL connected while calculating VTH.

02

Opening the ideal voltage source instead of shorting it when deactivating it.

03

Using R1 + R2 for RTH even though the zeroed source makes them parallel.

04

Treating Norton as an approximation instead of an exactly equivalent terminal model.

05

Comparing internal branch currents between equivalent models; only terminal behavior is guaranteed to match.

Reference

Reference result

Reveal only after completing your own derivation.

Reveal reference result
VTH = 8.000 VRTH = 2.000 kΩIN = 4.000 mAVL = 5.612 VIL = 1.194 mA
08

Evidence earned

The useful evidence is not that you saw the theorem; it is that you can derive, transform and verify the port model.

Derivation

Correct VTH, RTH and IN with stated source-deactivation reasoning.

Equivalence

Same VL and IL obtained from the original, Thévenin and Norton forms.

Explanation

Clear statement of what terminal equivalence does and does not imply.

Simulation

Optional MAJAL DC verification of all three circuits.