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E-001Foundational10–20 min

Loaded voltage divider

See why a voltage divider stops behaving ideally when the next circuit draws current.

PrerequisitesNone
Target skillselectronics.dc
LanguageOriginal curated content · English
01

Engineering problem

A 10 V source drives a divider made from R1 = 10 kΩ and R2 = 10 kΩ. First find the unloaded output voltage. Then connect RL = 10 kΩ from VOUT to ground and predict the new voltage before simulating anything.

Given valuesVs = 10 VR1 = 10 kΩR2 = 10 kΩRL = 10 kΩ

Canonical circuit under test

Generated from a language-neutral Circuit IR rather than drawn by hand. Visible connectivity is reconstructed from geometry and compared with the source netlist before rendering.

ERC + connectivity verified
Loaded voltage divider+−VS10 VR110 kΩR210 kΩRL10 kΩVINVOUTGND
02

What this exercise should prove

01

Apply KCL/Ohm-law reasoning to a loaded network.

02

Recognize that the load is in parallel with the lower divider resistor.

03

Quantify loading error rather than only saying that the output decreases.

04

Compare an analytical prediction with a DC simulation and, optionally, a real measurement.

03

Understand → Calculate → Simulate → Measure → Explain

01

Understand

Identify what changes physically when RL is connected: the source now supplies an additional current path.

02

Calculate

Reduce R2 || RL first, then use the divider relation on the equivalent network.

03

Simulate

Build the same circuit in MAJAL and run a DC operating-point calculation. Compare VOUT with your analytical value.

04

Measure

Optional: build the divider and deliberately add a 10 kΩ load. Record source voltage, VOUT and resistor tolerances.

05

Explain

Explain the discrepancy between loaded and unloaded cases in terms of finite output resistance and current demand.

04

Questions

  1. What is VOUT before RL is connected?
  2. What equivalent resistance replaces R2 after RL is connected?
  3. What is the new VOUT?
  4. What is the percentage loading error relative to the unloaded case?
  5. What condition on RL would make the divider behave approximately ideally?
Hints

Progressive hints

Reveal hint 1

RL and R2 connect between the same two nodes.

Reveal hint 2

Compute Rlower = R2 || RL before using the divider equation.

Reveal hint 3

With equal 10 kΩ resistors, R2 || RL = 5 kΩ.

05

MAJAL stage

The future .majalx package will open this circuit directly, preserve the exercise ID and check the engineering quantities without revealing the solution first.

MAJAL package coming
Future checksVOUT(no load) ≈ 5.000 VR2 || RL ≈ 5.000 kΩVOUT(loaded) ≈ 3.333 Vloading error ≈ −33.33 %
06

Common misconceptions

01

Adding R2 and RL in series even though they share both nodes.

02

Keeping VOUT = Vs·R2/(R1+R2) after attaching the load.

03

Reporting only the simulated number without explaining why it changed.

Reference

Reference result

Use this only after making your own attempt.

Reveal reference result
VOUT,0 = 5.000 VR2 || RL = 5.000 kΩVOUT,L = 3.333 VError = -33.33 %Ideal-loading condition: RL ≫ R2 (more precisely, RL should be large compared with the divider output resistance for the required error).
07

Evidence earned

The platform should reward what you demonstrate, not the fact that you opened the exercise.

Calculation

Correct unloaded and loaded analytical results.

Simulation

MAJAL DC result consistent with the analytical circuit.

Explanation

Clear physical explanation of loading and its validity condition.

Measurement · optional

Raw measured values + conditions + comparison to theory.